library verilog;
use verilog.vl_types.all;
entity key_update is
    port(
        data_o          : out    vl_logic_vector(79 downto 0);
        data_i          : in     vl_logic_vector(79 downto 0);
        round_counter   : in     vl_logic_vector(4 downto 0)
    );
end key_update;
